Dr. Feras Al-Hawari finished his Ph.D. degree in ECE from Northeastern University in June 2007. His dissertation was entitled Application-level QoS management system for network computing. For his Ph.D. dissertation he developed a QoS management framework in the context of the JavaPorts project in order to: (1) automate the mapping of a network computing (NC) application onto networks of workstations (NOWs) at startup time, and (2)facilitate application-level adaptation for performance and fault tolerance at run time. His dissertation committee included: Prof. Elias Manolakos (advisor), Prof. David Kaeli and Prof. Waleed Meleis. He completed his MS degree in CE from Florida Institute of Technology in May 1995. In addition, he received a BS degree in ECE from Jordan University of Science and Technology in June 1993.

He joined Cadence Design Systems in September 1995. Cadence is the number one player worldwide in developing Electronic Design Automation (EDA) software to design integrated circuits (ICs) and printed circuit boards (PCBs). He is currently a senior member of consulting staff (SMCS) in the Silicon-Package-Board (SPB) high-speed R&D group. His responsibilities include: (1) conducting research in the following areas: circuit simulation, device and interconnect modeling, and signal integrity (SI) analysis; (2) designing, developing, and testing new functionality within the Allegro PCB SI suite of tools; (3) providing consulting on: software architecture, core technologies, PCB design flows, and PCB analysis tools like SpecctraQuest and SigXplorer. Recently, he architected and automated the post-layout analysis flow for source synchronous bus interfaces (e.g., dual data rate memory interfaces such as DDR2 and DDR3). Moreover, he implemented methods for the transient simulation of scattering parameters and lossy multi-conductor transmission lines.

His research interests include: high-speed PCB design and analysis, EDA tools development, circuit simulation, signal integrity analysis, device and interconnect modeling, numerical methods, network protocols and security, distributed and cloud computing, database and web design, as well as software engineering.

He has two pending patents and several industry/academic publications. He served on the technical program committee of the Cadence technical conference (CTC). Moreover, he served as a reviewer for a number of academic journals and conferences such as the IEEE transactions on Advanced Packaging, the IEEE international conference on acoustics, speech, and signal processing (ICASSP) and the IASTED international conference on parallel and distributed computing and systems (PDCS). In addition, he participated in various joint research projects between Cadence and several renowned companies (e.g., IBM, Intel, Micron and Altera) and academic institutions (e.g., University of Illinois at Urbana-Champaign and Georgia Institute of Technology).

He regularly interacts with PCB and I/O designers to understand the design challenges they are facing in order to develop EDA tools that are easy to use and shorten the design cycle. Furthermore, he is a software architect with excellent design and development skills as well as practical experience in large-scale sequential, multithreaded, and distributed software projects. He has over 15 years of experience in the software development cycle - from the product requirement, functional and design specification to the development, testing, delivery and maintenance phases.

He considers himself a researcher, educator, team leader, hard worker, and fast learner. He adores embarking on new and challenging projects and has the necessary academic background and practical skills to investigate, identify, and solve many research problems in the fields of electrical, computer and software engineering.

Recent advances in IC fabrication technology as well as computer and telecommunication systems led to electronic designs that operate in the multi Gbit/s range. At high operational frequencies, passive structures (e.g. interconnect, via, wire-bond, solder ball) on printed circuit boards (PCBs) and IC packages directly affect the signal integrity (due to skin, reflection and crosswalk effects). Hence the accurate simulation of such designs requires modeling the high frequency behavior of passive elements. Frequency dependent scattering parameters (S-parameters) are most suitable to characterize circuit elements over a wide bandwidth. They relate incident and reflected traveling waves at the external ports of a circuit network and they can be conveniently obtained via measurements or 3D full-wave electromagnetic field solutions. However, the delay (e.g. setup and hold times) and noise (e.g. overshoot and undershoot) margins of a design are derived from transient time domain simulations. My research at Cadence Design Systems focused on efficient and accurate SPICE-level time domain simulation of frequency dependent elements.

We have investigated and implemented three methods to model and simulate a network black box characterized by frequency dependent data such as S, Y or Z parameters. The first method is based on obtaining the impulse response of the linear system (by calculating the Inverse Fast Fourier Transform IFFT of the frequency domain response) and then using direct convolution to find the time domain currents/voltages at the external ports. In the second method, we used a state of the art approximation technique to reduce the complexity of the direct convolution method from O(N²) to O(Nlog(N)), where N is proportional to the number of time steps in a transient simulation. The third method has an O(N) complexity and is based on using the vector fitting method to obtain a pole/residue (partial fraction) representation (i.e. transfer function) of the network. Then state-space representations or indirect convolution formulas are formulated to obtain the modified nodal analysis (MNA) matrix stamps that are used to perform the transient simulation. In each of the previous methods, the passivity and causality of the models is checked and preserved.

Moreover, we have developed an efficient and accurate algorithm to model and simulate coupled transmission lines characterized by frequency dependent RLGC matrices. The experimental results showed the robustness and accuracy of this method relatively to the W-element approach that is used to simulate transmission lines in many commercial circuit simulators such as HSPICE and SPECTRE.

A Network of Workstations (NOW) is an attractive parallel processing platform for tackling compute intensive problems. The wide availability of inexpensive PCs as well as off-the-shelf fast network technologies allow a NOW to offer a much better cost/performance ratio than supercomputers. Despite this reality, building distributed component-based applications for a NOW is still a painstaking experience. Frameworks and tools that can help designers to model, simulate, build, and run efficiently coarse grain parallel applications will certainly contribute to the growth of NOW's popularity and user base.

The NOW resources are usually heterogeneous and shared, making the system's state quite dynamic. Hence, a network computing (NC) application that exhibits performance gains under light load conditions (relatively to a sequential program realization) may not enjoy any speedup in the same environment under heavy load conditions. Therefore, if the objective is to deliver a targeted Quality of Service (QoS) level to an application (e.g., in terms of expected completion time or speedup), the system's state should be used in finding the best acceptable mapping of the parallel application's tasks to the available NOW resources before the application is launched (i.e., at startup time). Furthermore, the application should remain resource state aware and possibly adapt itself accordingly in order to keep meeting its QoS demands at runtime. My Ph.D. dissertation addressed the design and implementation of an end-to-end application-level QoS management system with a startup and a runtime component.

The startup component enables the developer of a NC application to run various QoS sessions in order to find an acceptable tasks-to-machines allocation strategy that meets user-defined QoS targets before the application is launched. It allows the developer to focus on task decomposition and interaction issues rather than on application configuration. Its basic features are: (1) QoS GUI, (2) resource monitoring, (3) performance estimation method, (4) application and network modeling, and (5) mapping heuristic. The QoS GUI is used to setup and deploy the various system modules and to run suitable QoS sessions. The scalable and non-intrusive monitoring system gathers resource information and makes it available to the other modules. The performance estimator predicts the overall running time of a given mapping based on application and network models as well as resource state information. The scheduler uses a mapping heuristic and the performance estimator to find a mapping that satisfies the desired QoS demands. Furthermore, the system is self contained and does not rely on third party frameworks for job submission or resource monitoring. It uses the existing JavaPorts framework to deploy the application tasks on the desired machines.

The runtime component provides a NC application with a QoS service that enables application-driven adaptation for performance and fault tolerance. The QoS service is associated with lightweight middleware that only monitors the state of the tasks as well as the attributes of the machines and logical network links used by the application it is servicing. The middleware is efficient because it does not waste cycles for monitoring unused resources. Moreover, it is automatically and transparently configured, launched, and terminated along with the companion application. The QoS service is made available to an application task via a simple to use and anonymous QoS API. In anonymous communications the name (and port) of the destination task does not need to be provided explicitly in the QoS API method call, which allows re-configuring the application tasks to run on a new set of machines without the need to re-code any part of the application logic (i.e., task location transparency). For example, the QoS API can be used to implement a dynamic application-level scheduler that can find more efficient assignments than its resource-unaware counterpart. Furthermore, a Manager-Worker application may use the fault tolerance QoS API to adapt for Worker faults (e.g., crash) in order to prevent application deadlock.